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n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 preliminary this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results. 1850 ramtron drive, colorado springs, co 80921 (800) 545-fram, (719) 481-7000 rev. 1.81 aug. 2009 page 1 of 12 fm20l08 1mbit bytewide fram memory ? industrial temp. features 1mbit ferroelectric nonvolatile ram ? organized as 128kx8 ? unlimited read/write cycles ? nodelay? writes ? page mode operation to 33mhz ? advanced high-reliability ferroelectric process sram replacement ? jedec 128kx8 sram pinout ? 60 ns access time, 350 ns cycle time system supervisor ? low voltage monitor drives external /lvl signal ? write protects memory for low voltage condition superior to battery-backed sram modules ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration ? resistant to negative voltage undershoots low power operation ? 3.3v +10%, -5% power supply ? 22 ma active current industry standard configurations ? industrial temperature -40 c to +85 c ? 32-pin ?green?/rohs tsop (-tg) description the fm20l08 is a 128k x 8 nonvolatile memory that reads and writes like a standard sram. a ferroelectric random access memory or fram is nonvolatile, which means that data is retained after power is removed. it provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed sram (bbsram). fast write timing and unlimited write endurance make fram superior to other types of memory. in-system operation of the fm20l08 is very similar to other ram devices and can be used as a drop-in replacement for standard sram. read and write cycles may be triggered by /ce or simply by changing the address. the fram memory is nonvolatile due to its unique ferroelectric memory process. these features make the fm20l08 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an sram. the fm20l08 includes a voltage monitor function that monitors the power supply voltage. it asserts an active-low signal that indicates the memory is write- protected when v dd drops below a critical threshold. when the /lvl signal is low, the memory is protected against an inadvertent access and data corruption. device specifications are guaranteed over the industrial temperature range -40c to +85c. pin configuration ordering information FM20L08-60-TG* 60 ns access, 32-pin ?green?/rohs tsop * end of life. last time buy nov. 2009. tsop-i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 we dnu a15 vdd lvl a16 a14 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a10 ce dq7 dq6 dq5 dq4 dq3 vss dq2 dq1 dq0 a0 a1 a2 a3
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 2 of 12 address latch ce control logic we row decoder a(16:3) a(2:0) i/o latch & bus driver oe dq(7:0) 16k x 64 f-ram array vdd monitor vdd lvl a(16:0) write protect . . . column decoder . . . figure 1. block diagram pin description pin name type pin description a(16:0) input address inputs: the 17 address lines select one of 131,072 bytes in the fram array. the address value is latched on the falling edge of /ce. addresses a(2:0) are used for page mode read and write operations. /ce input chip enable inputs: the device is selected and a new memory access begins when /ce is low. the entire address is latched internally on the falling edge of chip enable. subsequent changes to the a(2:0) address inputs allow page mode operation. /we input write enable: a write cycle begins when /we is asserted. the rising edge causes the fm20l08 to write the data on the dq bus to the fram array. the falling edge of /we latches a new column address for fast page mode write cycles. /oe input output enable: when /oe is low, the fm20l08 drives the data bus when valid data is available. deasserting /oe high tri-states the dq pins. dq(7:0) i/o data: 8-bit bi-directional data bus for accessing the fram array. /lvl output low voltage lockout: when the voltage monitor detects that v dd is below v tp , the /lvl pin will be asserted low. while /lvl is low, the memory array cannot be accessed which prevents a low voltage write from corrupting data. when v dd is within its normal operating limits, the /lvl signal will be pulled high. dnu - do not use: this pin should be left unconnected. vdd supply supply voltage: 3.3v vss supply ground
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 3 of 12 functional truth table /ce /we a(16:3) a(2:0) operation h x x x standby/idle h v v read l h no change change page mode read l h change v random read l v v /ce-controlled write l x v /we-controlled write 2 l no change v page mode write 3 x x x starts precharge notes: 1) h=logic high, l=logic low, v=valid address, x=don?t care. 2) /we-controlled write cycle begins as a read cycle and a(16:3) is latched then. 3) addresses a(2:0) must remain stable for at least 15 ns during page mode operation. 4) for write cycles, data-in is latched on the rising edge of /ce or /we, whichever comes first.
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 4 of 12 overview the fm20l08 is a bytewide fram memory logically organized as 131,072 x 8 and is accessed using an industry standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers page mode operation which provides higher speed access to addresses within a page (row). an access to a different page requires that either /ce transitions low or the upper address a(16:3) changes. memory operation users access 131,072 memory locations with 8 data bits each through a parallel interface. the fram array is internally organized as 16k rows of 64 bits each. within each row (page) there are 8 column locations, which allow fast access in page mode operation. once an initial address has been latched by the falling edge of /ce, subsequent column locations may be accessed without the need to toggle /ce. when /ce is deasserted high, a precharge operation begins. writes occur immediately at the end of the access with no delay. the /we pin must be toggled for each write operation. read operation a read operation begins on the falling edge of /ce. the falling edge of /ce causes the address to be latched and starts a memory read cycle if /we is high. data becomes available on the bus after the access time has been satisfied. once the address has been latched and the access completed, a new access to a random location (different row) may begin while /ce is still low. the minimum cycle time for random addresses is t rc . note that unlike srams, the fm20l08?s /ce-initiated access time is faster than the address cycle time. the fm20l08 will drive the data bus only when /oe is asserted low and the memory access time has been satisfied. if /oe is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is inactive, the data bus will remain hi-z. write operation writes occur in the fm20l08 in the same time interval as reads. the fm20l08 supports both /ce- and /we-controlled write cycles. in both cases, the address is latched on the falling edge of /ce. in a /ce-controlled write, the /we signal is asserted prior to beginning the memory cycle. that is, /we is low when /ce falls. in this case, the device begins the memory cycle as a write. the fm20l08 will not drive the data bus regardless of the state of /oe as long as /we is low. input data must be valid when /ce is deasserted high. in a /we-controlled write, the memory cycle begins on the falling edge of /ce. the /we signal falls some time later. therefore, the memory cycle begins as a read. the data bus will be driven if /oe is low, however it will hi-z once /we is asserted low. the /ce- and /we-controlled write timing cases are shown on page 9. in the write cycle timing 2 diagram, the data bus is shown as a hi-z condition while the chip is write-enabled and before the required setup time. although this is drawn to look like a mid-level voltage, it is recommended that all dq pins comply with the minimum v ih /v il operating levels. write access to the array begins on the falling edge of /we after the memory cycle is initiated. the write access terminates on the rising edge of /we or /ce, whichever comes first. a valid write operation requires the user to meet the access time specification prior to deasserting /we or /ce. data setup time indicates the interval during which data cannot change prior to the end of the write access (/we or /ce high). unlike other nonvolatile memory technologies, there is no write delay with fram. since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the fm20l08 provides the user fast access to any data within a row element. each row has eight column locations. an access can start anywhere within a row and other column locations may be accessed without the need to toggle the /ce pin. for page mode reads, once the first data byte is driven onto the bus, the column address inputs a(2:0) may be changed to a new value. a new data byte is then driven to the dq pins. for page mode writes, the first write pulse defines the first write access. while /ce is low, a subsequent write pulse along with a new column address provides a page mode write access. precharge operation the precharge operation is an internal condition in which the state of the memory is prepared for a new access. precharge is user-initiated by driving the /ce signal high. it must remain high for at least the minimum precharge time t pc .
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 5 of 12 supply voltage monitor an internal voltage monitor circuit continuously checks the v dd supply voltage. when v dd is below the specified threshold v tp , the monitor asserts the /lvl signal to an active-low state. the fm20l08 locks out access to the memory when v dd is below the trip voltage. this prevents the system from accessing memory when v dd is too low and inadvertently corrupting the data. the /lvl signal should not be used as a system reset signal because the system host may attempt to write data to the fm20l08 below its specified operating voltage. the /lvl pin may be used as a status indicator that the memory is locked out. on power up, the /lvl signal will begin in a low state signifying that v dd is below the v tp threshold. it will remain low as long as v dd is below that level. once v dd rises above v tp , a hold-off timer will begin creating the delay t pulv . once this delay has elapsed, the /lvl signal will go high or inactive. at this time the memory can be accessed. the memory is ready for access prior to t pu as shown in the electrical specifications section. the /lvl signal will remain high until v dd drops below the threshold. sram drop-in replacement the fm20l08 has been designed to be a drop-in replacement for standard asynchronous srams. the device does not require /ce to toggle for each new address. /ce may remain low indefinitely while v dd is applied. when /ce is low, the device automatically detects address changes and a new access is begun. it also allows page mode operation at speeds up to 33mhz. although /ce may be held low for extended periods of time, the pin should not be tied to ground or held low during power cycles. /ce must be pulled high and allowed to track v dd during powerup and powerdown cycles. it is the user?s responsibility to ensure that chip enable is high to prevent incorrect operation. figure 2 shows a pullup resistor on /ce which will keep the pin high during power cycles assuming the mcu/mpu pin tri-states during the reset condition. the pullup resistor value should be chosen to ensure the /ce pin tracks v dd yet a high enough value that the current drawn when /ce is low is not an issue. figure 2. use of pullup resistor on /ce for applications that require the lowest power consumption, the /ce signal should be active only during memory accesses. due to the external pullup resistor, some supply current will be drawn while /ce is low. when /ce is high, the device draws no more than the maximum standby current i sb . the fm20l08 is backward compatible with the 256kbit fm18l08 device. so, operating the fm20l08 with /ce toggling low on every address is perfectly acceptable. ce we oe a(16:0) dq fm20l08 v dd mcu/ mpu r
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 6 of 12 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +5.0v v in voltage on any signal pin with respect to v ss -1.0v to +5.0v and v in < v dd +1v t stg storage temperature -55 c to +125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-b) - charged device model (jedec std jesd22-c101-a) - machine model (jedec std jesd22-a115-a) 3kv 750v 200v package moisture sensitivity level msl-2 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to +85 c, v dd = 3.3v +10%, -5% unless otherwise specified) symbol parameter min typ max units notes v dd power supply 3.135 3.3 3.63 v i dd v dd supply current - 22 ma 1 i sb standby current ? cmos - 25 a 2 v tp v dd trip point to assert (deassert) /lvl 2.7 - 3.0 v 3 i li input leakage current 1 a 4 i lo output leakage current 1 a 4 v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.6 v v oh output high voltage ( i oh = -1.0 ma) 2.4 - v v ol output low voltage ( i ol = 2.1 ma) - 0.4 v 5 notes 1. v dd = 3.6v, /ce cycling at minimum cycle time. all inputs at cmos levels (0.2v or v dd -0.2v), all dq pins unloaded. 2. v dd = 3.6v, /ce at v dd , all other pins at cmos levels (0.2v or v dd -0.2v). 3. this is the v dd trip voltage at which /lvl is asserted or deasserted. when v dd rises above v tp , /lvl will be deasserted after satisfying t pulv . when v dd drops below v tp , /lvl will be asserted after satisfying t pdlv . 4. v in , v out between v dd and v ss . 5. for the /lvl pin, the test condition is i ol = 80 a when v dd is between 3.135v and 1.2v. the state of the /lvl pin is not guaranteed when v dd is below 1.2v.
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 7 of 12 read cycle ac parameters (t a = -40 c to +85 c, c l = 30 pf, v dd = 3.3v +10%, -5% unless otherwise specified) -60 symbol parameter min max units notes t rc read cycle time 350 - ns t ce chip enable access time - 60 ns t a a address access time - 350 ns t oh output hold time 50 - ns t aap page mode address access time - 25 ns t ohp page mode output hold time 5 - ns t c a chip enable active time 60 - ns t pc precharge time 290 - ns t as address setup time (to /ce low) 5 - ns t ah address hold time (/ce-controlled) 60 - ns t oe output enable access time - 10 ns t hz chip enable to output high-z - 15 ns 1 t ohz output enable high to output high-z - 15 ns 1 write cycle ac parameters (t a = -40 c to +85 c, v dd = 3.3v +10%, -5% unless otherwise specified) -60 symbol parameter min max units notes t wc write cycle time 350 - ns t c a chip enable active time 60 - ns t cw chip enable to write enable high 60 - ns t pc precharge time 290 - ns t pwc page mode write enable cycle time 30 - ns t wp write enable pulse width 15 - ns t as address setup time (to /ce low) 5 - ns t ah address hold time (/ce-controlled) 60 - ns t asp page mode address setup time (to /we low) 5 - ns t ahp page mode address hold time (to /we low) 15 - ns t wlc write enable low to /ce high 25 - ns t wl a write enable low to a(16:3) change 25 - ns t awh a(16:3) change to write enable high 350 - ns t ds data input setup time 20 - ns t dh data input hold time 0 - ns t wz write enable low to output high z - 15 ns 1 t wx write enable high to output driven 5 - ns 1 t ws write enable to /ce low setup time 0 - ns 1,2 t wh write enable to /ce high hold time 0 - ns 1,2 notes 1 this parameter is characterized but not 100% tested. 2 the relationship between /ce and /we determines if a /ce- or /we-controlled write occurs. power cycle timing (t a = -40 c to +85 c, v dd = 3.3v +10%, -5% unless otherwise specified) symbol parameter min max units notes t pulv power up to /lvl inactive time (v tp to /lvl high) 0 5 ms t pdlv power down to /lvl active time (v tp to /lvl low) 0 15 s t pu power up (/lvl high) to first access time 0 - s t pd last access (/ce high) to power down (v dd min) 0 - s t vr v dd rise time 50 - s/v 1 t vf v dd fall time 100 - s/v 1 notes 1 slope measured at any point on v dd waveform.
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 8 of 12 data retention (v dd = 3.3v +10%, -5% ) parameter min max units notes data retention 10 - years capacitance (t a = 25 c , f=1 mhz, v dd = 3.3v) symbol parameter min max units notes c i/o input/output capacitance (dq) - 8 pf 1 c in input capacitance - 6 pf 1 notes 1. this parameter is characterized and not 100% tested. ac test conditions input pulse levels 0 to 3v input rise and fall times 3 ns input and output timing levels 1.5v output load capacitance 30 pf read cycle timing 1 (/ce low, /oe low) a(16:0) dq(7:0) t rc t oh t aa t oh read cycle timing 2 (/ce-controlled) ce a(16:0) oe dq(7:0) t as t ce t ca t pc t oe t ohz t hz t ah
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 9 of 12 page mode read cycle timing although sequential column addressing is shown, it is not required. write cycle timing 1 (/we-controlled, /oe low) write cycle timing 2 (/ce-controlled) note: see write operation section for detailed description (page 4).
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 10 of 12 write cycle timing 3 (/ce low) page mode write cycle timing ce a(16:3) we t ca t pc dq(7:0) t cw a(2:0) col 0 col 1 data 0 col 2 t as t ds data 1 t wp t dh data 2 oe t ahp t pwc t wlc t asp t ah although sequential column addressing is shown, it is not required. power cycle timing
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 11 of 12 mechanical drawing 32-pin shrunk tsop-i (8.0 x 13.4 mm) all dimensions in millimeters tsop package marking scheme legend: xxxxxx= part number, sp= speed/package/temp (blank=ind., c=extended) r=rev code, yy=year, ww=work week, llllll= lot code examples: ?green? tsop package, industrial temp, b rev., year 2006, work week 44, lot 60011tg ramtron fm20l08-60tg b064460011tg ramtron xxxxxxx-sp ryywwllllll
n o t r e c o mm e n d e d f o r n e w d e s i g n s r e pl a c e m e n t: f m 2 8 v 1 0 0 fm20l08 - industrial temp. rev. 1.81 aug. 2009 page 12 of 12 revision history revision date summary 0.6 1/30/04 added vdd fall time spec. changed power cycle timing diagram. added t awh write timing spec. added typ value to v tp in dc operating table. changed software write-protect scheme. changed /lvl to output-only pin. modified block diagram, pin description and dc operating tables. modified package drawing title. 0.61 5/20/04 changed t wx , t aap , and t awh specs. added t ah to write cycle parameters table. changed input rise/fall time ac test condition. changed t vf units. added ?green? package. 0.7 9/3/04 reduced to one speed grade and changed to -60 speed grade. supply voltage 3.3v +10%, -5%. temp range 0 to +85c. 0.8 12/20/04 temp range -40 to +85c. changed ac timing parameters. changed part number/ordering information. 1.0 3/25/05 changed to preliminary status. 1.1 5/23/05 added ?green? packaging option. added marking scheme. 1.2 6/6/05 removed ?t packaging option. 1.3 8/15/05 changed address setup and i dd specs. added t vr parameter. added note about /ce high during power cycles. modified power cycle timing diagram and added timing parameters. removed references to the use of /lvl as a system reset signal. changed temperature limits. 1.4 10/18/05 changed i sb . changed v tp limits. added note to power cycle timing table. rewrote text describing use of pullup resistor. 1.5 2/9/06 order device with or without software wp. changed t pulv to 5ms. added esd and msl ratings. 1.6 6/12/06 changed specs to industrial temperature. devices with date codes 0605 thro ugh 0620 comply with this datasheet revision. 1.7 8/21/06 changed i sb spec. updated esd ratings. removed note 2 from power cycle timing table. devices with date codes 0624 and beyond comply with this datasheet revision. 1.71 4/9/07 changed package marking scheme. updated esd machine model and msl ratings. 1.72 5/10/07 added pcb footprint to package drawing. 1.8 5/6/2008 removed ?tg1 (software write protect) ordering number. 1.81 8/5/2009 not recommended for new designs. last time buy nov. 2009. as a replacement, use the fm28v100 device.

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